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ML6554
3A Bus Termination Regulator
Features
* Can source and sink up to 3A, no heat sink required * Integrated Power MOSFETs * Generates termination voltages for DDR SDRAM, SSTL-2 SDRAM, SGRAM, or equivalent memories * Generates termination voltages for active termination schemes for DDR SDRAM, GTL+, Rambus, VME, LV-TTL, HSTL, PECL and other high speed logic * VREF input available for external voltage divider * Separate voltages for VCCQ and PVDD * Buffered VREF output * VOUT of 3% or less at 3A * Minimum external components * Shutdown for standby or suspend mode operation * 0 to +70C and -40 to +85C temperature ranges available * Thermal Shutdown 130C
Description
The ML6554 switching regulator is designed to convert voltage supplies ranging from 2.3V to 4V into a desired output voltage or termination voltage for various applications. The ML6554 can be implemented to produce regulated output voltages in two different modes. In the default mode, when the VREF pin is open, the ML6554 output voltage is 50% of the voltage applied to VCCQ. The ML6554 can also be used to produce various user-defined voltages by forcing a voltage on the VREFIN pin. In this case, the output voltage follows the input VREFIN voltage. The switching regulator is capable of sourcing or sinking up to 3A of current while regulating an output VTT voltage to within 3% or less. The ML6554, used in conjunction with series termination resisitors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. The voltage output of the regulator can be used as a termination voltage for other bus interface standards such as DDR SDRAM, SSTL, CMOS, RambusTM, GTL+, VME, LV-CMOS, LV-TTL, HSTL and PECL.
Block Diagram
15
VCCQ
16
AVCC
14
VREFOUT
1
9 VDD VDD
12
SHDN
2
PVDD1
7
PVDD2 VL1 (VOUT) 3
OSCILLATOR/ RAMP GENERATOR - 200k + VREF BUFFER VREFIN 11 200k AGND 13 + - - R + ERROR AMP RAMP COMPARATOR Q S Q
6 VL2 (VOUT)
VFB 10 8
DGND 4
PGND1 5
PGND2
REV. 1.1.3 3/8/02
ML6554
PRODUCT SPECIFICATION
Pin Configuration
ML6554 16-Pin PSOP (U16)
VDD PVDD1 VL1 PGND1 PGND2 VL2 PVDD2 DGND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 AVCC VCCQ VREFOUT AGND SHDN VREFIN VFB VDD
TOP VIEW
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VDD PVDD1 VL1 PGND1 PGND2 VL2 PVDD2 DGND VDD VFB VREFIN SHDN AGND VREFOUT VCCQ AVCC Digital supply voltage Voltage supply for internal power transistors Output voltage/ inductor connection Ground for output power transistors Ground for output power transistors Output voltage/inductor connection Voltage supply for internal power transistors Digital ground Digital supply voltage Input for external compensation feedback Input for external reference voltage Shutdown active low. CMOS input level Ground for internal reference voltage divider Reference voltage output Voltage reference for internal voltage divider Analog voltage supply Function
2
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter PVDD Voltage on Any Other Pin Average Switch Current (IAVG) Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (JC)(Note 2) Output Current, Source or Sink Min. GND - 0.3 Max. 4.5 VIN + 0.3 3.0 150 150 150 2 3.0 Units V V A C C C C/W A
-65
Operating Conditions
Parameter Temperature Range, CU suffix Temperature Range, IU suffix PVDD Operating Range VCCQ Operating Range Min. 0 -40 2.0 1.4 Max. 70 +85 4.0 4.0 Units C C V V
Electrical Characteristics
Unless otherwise specified, AVCC = VDD = PVDD = 3.3V 10%, TA = Operating Temperature Range (Note 1) Symbol Parameter Switching Regulator VTT Output Voltage, SSTL_2 (See Figure 1) Conditions IOUT = 0, VREF = open IOUT = 3A, VREF = open VREFOUT Internal Resistor Divider IOUT = 0 Min. Typ. Max. Units V V V V V V V V V k kHz mV A mA mA mA mA A mA
ZIN
VOFFSET Supply IQ Quiescent Current
VREF Reference Pin Input Impedance Switching Frequency Offset Voltage VTT - VREFOUT
VCCQ = 2.3V 1.12 1.15 1.18 VCCQ = 2.5V 1.22 1.25 1.28 VCCQ = 2.7V 1.32 1.35 1.38 VCCQ = 2.3V 1.09 1.15 1.21 VCCQ = 2.5V 1.19 1.25 1.31 VCCQ = 2.7V 1.28 1.35 1.42 VCCQ = 2.3V 1.139 1.15 1.162 VCCQ = 2.5V 1.238 1.25 1.263 VCCQ = 2.7V 1.337 1.35 1.364 VCCQ = 0 100 650
AVCC = 2.5V No Load VCCQ = 2.5 IOUT = 0, no load VCCQ = 2.5V IVCCQ IAVCC IAVCC SD IVDD IVDD SD IPVDD
-20 6 0.5 0.2 0.25 0.2 100 3
20 10 1.0 0.5 1.0 1.0 250
Buffer IREF
Output Load Current
Notes 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 2. Infinite heat sink REV. 1.1.3 3/8/02 3
ML6554
PRODUCT SPECIFICATION
Functional Description
This switching regulator is capable of sinking and sourcing 3A of current without an external heatsink. The ML6554 uses a power surface mount package (PSOP) that includes an integrated heat slug. The heat can be piped through the bottom of the device and onto the PCB (Figure 1). The ML6554 integrates two power MOSFETs that can be used to source and sink 3A of current while maintaining a tight voltage regulation. Using the external feedback, the output can be regulated well within 3% or less, depending on the external components chosen. Separate voltage supply inputs have been added to accommodate applications with various power supplies for the databus and power buses, see Figure 2.
Output voltage can also be selected by forcing a voltage at the VREFIN pin. In this case, the output voltage follows the voltage at the VREFIN input. Simple voltage dividers can be used this case to produce a wide variety of output voltages between 0.7V and VDD-0.7V.
VREF Input and Output
The VREFIN input can be used to force a voltage at the outputs (Inputs section, above). The VREFOUT pin is an output pin that is driven by a small output buffer to provide the VREF signal to other devices in the system. The output buffer is capable of driving several output loads. The output buffer can handle 3mA.
Other Supply Voltages
Several inputs are provide for the supply voltages: PVDD1, PVDD2, AVCC, and VDD. The PVDD1 and PVDD2 provide the power supply to the power MOSFETs. VDD provides the voltage supply to the digital sections, while AVCC supplies the voltage for the analog sections. Again, see the Applications section for recommendations.
Outputs
The output voltage pins (VL1, VL2) are tied to the databus, address, or clock lines via an external inductor. See the Applications section for recommendations. Output voltage is determined by the VCCQ or VREFIN inputs.
Inputs
The input voltage pins (VCCQ or VREFIN) determine the output voltages (VL1 or VL2) . In the default mode, where the VREFIN pin is floating, the output voltage is 50% of the VCCQ input. VCCQ can be the reference voltage for the databus.
Feedback Input
The VFB pin is an input that can be used for closed loop compensation. This input is derived from the voltage output. See application section for recommendation.
HEAT SLUG
Figure 1. Cutaway view of PSOP Package
4
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
Applications
Using the ML6554 for SSTL Bus Termination
The circuit schematic in Figure 2 shows a recommended approach for constructing a bus terminating solution for an SSTL-2 bus. This circuit can be used in PC memory and Graphics memory applications as shown in Figures 4 and 5. Note that the ML6554 can provide the voltage reference (VREF) and terminating voltages (VTT). Using the layout as shown in Figures 6, 7, and 8, and measuring the VTT performance using the test setup as described in Figure 9, the ML6554 delivered a VTT 20mV for 1A to 3A loads (see Figure 10). Table 1 provides a recommended parts list for the circuit in Figure 2.
Power Handling Capability of the PSOP Package
Using the board layout shown in Figures 6, 7, and 8; soldering the ML6554 to the board at zero LFPM the temperature around the package measured 55C for 3A loads. Note that a 1 ounce copper plane was used in the board construction. Airflow is not likely to be needed in the operation of this device (assuming a board layout similar to that described above). The power handling performance of the PSOP package is shown by a study of the package manufacturer for various airflow vs. JA conditions in Figure 11.
Bus Termination Solutions for Others Buses
Table 3 provides a summary of various bus termination VREF & VTT requirements. The ML6554 can be used for those applications.
2.5V TO 4V R2 100 R1 100 C9 0.1F C8 0.1F
R3 100k
C5 330F
C6 330F
U1 ML6554
TPI 1 2 VTT C1 820F F2V OS-CON TO SDRAMS L1 3.3H C3 0.1F 3 4 C2 0.1F C4 0.1F 5 6 7 8 VDD PVDD1 VL1 PGND1 PGND2 VL2 PVDD2 DGND AVCC VCCQ VREFOUT AGND SHDN VREFIN VFB VDD 16 15 14 13 12 11 10 9 SHDN VREFIN VCCQ VREFOUT
R4 100k C7 1nF GND
R5 1k GND
Figure 2.
REV. 1.1.3 3/8/02
5
ML6554
PRODUCT SPECIFICATION
2.5V TO 4V
C5 330F
C6 330F
U1 ML6554
1 C3 10F VTT C1 820F F2V OS-CON TO SDRAMS L1 3.3H 2 3 4 C2 0.1F 5 6 7 8 VDD PVDD1 VL1 PGND1 PGND2 VL2 PVDD2 DGND AVCC VCCQ VREFOUT AGND SHDN VREFIN VFB VDD 16 15 14 13 12 11 10 9
R3 100k
VCCQ VREFOUT
SHDN VREFIN
R1 100k C4 1nF GND
R2 1k GND
Figure 3. Alternate Application Circuit
An alternate application circuit for the ML6554 is shown in Figure 3. The number of external components is reduced compared to the circuit in Figure 2. This is achieved by replacing four, 0.1F bypass capacitors with one, low ESR, 10F ceramic capacitor placed right next to U1. Two 100 resistors are also eliminated. High value, surface-mount
MLC capacitors were not available when the original application circuit (Figure 2) was developed. Both application circuits offer the same electrical performance but that shown in Figure 2 has a reduced bill-of-materials. Table 2 shows the recommended parts list for the circuit of Figure 3.
6
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
168/184/208-PIN DIMM CONNECTORS AND SDRAM/SGRAM MODULES TERMINATION RESISTORS
PC CHIP SET NORTHBRIDGE
DATA LINE, CLOCK LINES, ADDRESS LINES, CONTROL LINES
TERMINATION RESISTORS
VTT
ML6554 VREF
Figure 4. Complete Termination Solution PC Main Memory (PC Motherboard)
SO DIMM AND MODULES TERMINATION RESISTORS SGRAM
3D GRAPHIC CHIP
DATA LINE, CLOCK LINES, ADDRESS LINES, CONTROL LINES
TERMINATION RESISTORS 2.5V VOLTAGE REGULATOR 5V OR 3.3V
VREF ML6554 VTT
AGP/PCI BUS
Figure 5. Complete Termination Solution Graphics Memory Bus - AGP Graphics Cards REV. 1.1.3 3/8/02 7
ML6554
PRODUCT SPECIFICATION
Figure 6. Top Silk
Figure 7. Top Layer
Figure 8. Bottom Layer
8
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
3.3V POWER SUPPLY
V
A
ACTIVE CLAMP
VDD VCCQ VCCQ SUPPLY ML6554 EVAL GND VTT CURRENT SOURCE/SINK POWER SUPPLY ITT
V
A
Figure 9. Test Circuit Setup
VTT VARIANCE WITH VDD@ITT (VCCQ 2.5V) TESTED WITH EVAL PCB 1.29 ITT 3A SINKING
2A SINKING 1.28 1A SINKING VTT (V)
0A SINKING 1.27 3A SOURCING
2A SOURCING 1.26 2.0
2.5
3.0 VDD (V)
3.5
4.0
1A SOURCING
Figure 10. VTT Performance for SSTL-2 Bus
REV. 1.1.3 3/8/02
9
ML6554
PRODUCT SPECIFICATION
Table 1. Recommend Parts List for SSTL-2 Termination Circuit in Figure 2.
Item Resistors 1 2 3 Capacitors 4 5 6 7 8 ICS 9 Magnetics 10
Qty 2 1 2 3 1 2 1 2 1
Description 1001210 SMD 1k 1210 SMD 100k1210 SMD 0.1F 1210 Film SMD 820F 2V Solid Elect. SMD 330F Tant 6.3V 100m 1nF 1210 Film SMD 0.1F 0805 Film ML6554 Bus Terminator Power SOP Package 3.3H 5A inductor SMD
Manufacturer / Part Number Panasonic/ERJ-8ENF1000V Panasonic/ERJ-8ENF1001V Panasonic/ERJ-8ENF1003V Panasonic/ECV3VB1E104K Panasonic/ECU-V1H104KBW Sanyo/2SV820M Os Con AVX/TPSE337M006R0100 Panasonic/ECU-V1H102KBM Panasonic/ECJ-2VF1C104Z ML6554CU or ML6554IU
Designator R1, R2 R5 R3, R4 C2, C8, C9 C1 C5, C6 C7 C3, C4 U1
1
Coilcraft/D03316P-332HC Pulse Eng./ P0751.332T Gowanda/SMP3316-331M XFMRS inc./XF0046-S4 Tektronics/131-4353-00 Sullins/PTC36SAAN (36 PINS)
L1
Other 11 12
1 1
Scope probe socket 12 Pin breakaway strip
TP1 I/O, standoffs
Table 2. Recommend Parts List for Figure 3.
Item Resistors 1 2 Capacitors 3 4 5 6 7 ICS 8 Magnetics 9
Qty 2 1 1 1 2 1 1 1
Description 100k 0805 SMD 1k 0805 SMD 0.1F, 1210 Film SMD 820F 2V Solid Elect. SMD 330F Tant 6.3V 100m 1nF 1210 Film SMD 10F 6.3V Ceramic ML6554 Bus Terminator Power SOP Package 3.3H 5A inductor SMD
Manufacturer / Part Number Panasonic/ERJ-8ENF1000V Panasonic/ERJ-8ENF1000V Panasonic/ECV3VB1E104K Panasonic/ECU-V1H104KBW Sanyo/2SV820M Os Con AVX/TPSE337M006R0100 Panasonic/ECU-V1H102KBM TDK/C2012X5R0J106M ML6554CU or ML6554IU
Designator R1, R3 R2 C2 C1 C5, C6 C4 C3 U1
1
Coilcraft/D03316P-332HC Pulse Eng./ P0751.332T Gowanda/SMP3316-331M XFMRS inc./XF0046-S4 Tektronics/131-4353-00 Sullins/PTC36SAAN (36 PINS)
L1
Other 10 11
1 1
Scope probe socket 12 Pin breakaway strip
TP1 I/O, standoffs
10
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
Vendor List
1. AVX 2. Sanyo 3. Tektronix 4. Coilcraft 5. Pulse 6. Gowanda 7. Xfmrs Inc. 8. Panasonic 9. Digikey (207) 282-5111 (619) 661-6835 (408) 496-0800 (847) 639-6400 (800) 797-8573 (716) 532-2234 (317) 834-1066 (714) 373-7366 (800) 344-4539
60
60
40 JA (C/W) 20 16Ld PSOP2 2.3x3.1mm PAD 1.9mm DIE 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 POWER (W) NATURAL CONVECTION JA TEST RESULTS 1.27mm PITCH PowerSOPTM 2 SLUG SOLDERED JA (C/W)
40
20
16Ld PSOP2 2.3x3.1mm PAD 1.9mm DIE @ 0.8 WATTS 0 0 100 200 300 400 500 AIR VELOCITY (LFPM) FORCED CONVECTION JA TEST RESULTS 1.27mm PITCH PowerSOPTM 2 SLUG SOLDERED
Figure 11. Graphical Results Summary - 1S2P Test Board
REV. 1.1.3 3/8/02
11
ML6554
PRODUCT SPECIFICATION
DRAWING NUMBER Applicable Jedec Spec Substrate Material Dimensions (LxW) (Overall) Dimensions (LxW) (Metallization) Dimensions (LxW) (Inner Planes) Thickness Pitch Stackup (# Signal Layers, # Cu Planes) Cu Trace Coverage (Signal Layer) Cu Coverage (Internal Layer) Trace Width (Spec/Measured) Trace Cu Thickness (Spec/Measured) Inner Cu Thickness (Spec/Measured) Build #
ENG-CB-1007 REV A JC 51-X (Note 1) (Proposed Spec) FR-4 114.3 x 76.2mm 55 x 65mm 73 x 73mm 1.6 mm 1.27mm 1S2P 12% 100% 235.525.5/288m 7014/67m 353.5/31m C1797
Note 1: Proposed Spec "Thermal Test Board with Two Internal Solid Copper Planes for leaded Surface Mount Packages".
Figure 12. Test Board Layout for JA vs. Airflow
Table 3. Termination Solutions Summary By Buss Type
Bus GTL+
Description Gunning Transceiver Bus Plus
Driving Method
VDDQ
VTT
VREF 1.0V2% Note 11
Fairchild Solutions ML6554CU; Mode: VREF Input = 1.5V, VCC = 5V
Industry System Components 300 to 500MHz Processor; PC Chipsets; GTLP 16xxx Buffers; Fairchild, Texas Instr. SSTL SDRAM; Hitachi, Fujitsu, NEC, Micro, Mitsubishi nDRAM, RAMBUS, Intel, Toshiba Processors or backplanes; LV-TTL SDRAM, EDO RAM
Open Drain 5v or 3.3V 1.5V10% Note 10 Note12
SSTL_2
Series Stub Terminated Logic for 2V
Symmetric Drive, Series Resistance
2.5V10%
0.5x (VDDQ) 3%
2.5V
ML6554CU or ML6553CS; Mode: VREF Input = Floating or Forced, VCC = 3.3V ML6553CS; Mode: VREF Input = Open, VCC = VDDQ ML6553CS; Mode: VREF Input = Open, VCC = VDDQ
RAMBUS
RAMBUS Signaling Logic Low Voltage TTL Logic or PECL or 3.3V VME
Open Drain
None Specified
2.5V
2.0V
LV-TTL
Symmetric Drive
3.310%
VDDQ/2
3.3V
12
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
Mechanical Dimensions
16-Pin PSOP
9.90 0.10 8.89 1.95 16 9 B 3.90 0.10 1.75 3.70 1 PIN ONE INDICATOR 1.27 8 0.51 0.35 0.25 M C B A 1.27 8.89 LAND PATTERN RECOMMENDATION SEE DETAIL A 0.25 0.19 7.50
A 0.60
6.00
2.50
7.40
3.50
(0.30)
1.75 MAX +0.05 1.45 -0.20 C 0.10 C +0.10 0.15 -0.05 0.50 0.25 X 45 GAGE PLANE
(R0.10) (R0.10) 8 0
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AC, ISSUE C, DATED MAY 1990. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS.
0.36
0.70 0.20 (1.04) DETAIL A
SCALE: 2:1
SEATING PLANE
REV. 1.1.3 3/8/02
13
ML6554
PRODUCT SPECIFICATION
Ordering Information
Part Number ML6554CU ML6554IU Temperature Range 0C to 70C -40C to +85C Package 16-Pin PSOP (U16) 16-Pin PSOP (U16)
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury of the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
3/8/02 0.0m 002 Stock#DS30006554 2001 Fairchild Semiconductor Corporation

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